Quick First Look: Xilinx ISE 10.1 Webpack

Introduction

Today, embedded engineers can spend vast amounts of time in front of their PC writing code to upload into their hardware design. In this first look, I wanted to take a few hours and explore Xilinx's ISE 10.1 Webpack software and see how quickly it would take me to create and flash a program that causes an LED to light up when I push a button into a CPLD. For this review, I am using a very simple Digilent XC2-XL CPLD Design Kit with a Xilinx CoolRunner II (XC2C256-7TQ144C) CPLD. I am using a basic Windows XP system with a parallel port JTAG.

Getting Started

Downloading Xilinx's ISE (Webpack) is a simple task. The only concern I had with the install is that this is what I call a “web installable product.” This means that you need to be connected to the Internet for the product to install. Lucky, Xilinx did provide a simple check box option where the installer would download all the files needed for an offline install. I did not test that feature.

When I first started up Xilinx ISE I noticed it had the familiar menu system such as “New Project” or open files found in many different types of IDE's. Unfortunately, that's where familiarity ends and uniqueness begins. For the most part, Xilinx divided their UI into three major parts Implementation, Behavioral Simulation, and Post-Fit Simulation. Each of the three parts are separated by a drop down panel and each have unique controls and tabs. This uniqueness is then merged into a panel which has all the controls for running the above system which all has different right click property options selectable by this panel. In short, it makes things really difficult to find.

One nice thing I like about ISE UI is that it uses fairly readable fonts and has a modern feel to it. For the most part, it also sticks to GUI based system so there is no real need to learn the command line for ISE. Xilinx also uses tabs extensively (a bit too much in some cases) so that you don't have to worry about having a dozen windows open. The added ability to comment blocks of code quickly is also a nice feature. This makes ISE feel more modern compared to some other hardware vendor IDE.

From what I can tell from ISE, it looks like Xilinx took several programs and built this IDE from it. Unfortunately, the integration between each program such as PACE (Floorplanning) and iMPACT (JTAG Programmer) with the main IDE still needs work. This is because the IDE opens a program like iMPACT and requires you to find the programmable file yourself.

Experiment

In this first look, I made a simple experiment which takes a button signal that goes through a NOT gate and into a light on the Digilent board using Verilog. 

module ButtonTestModule(Button, Light);

    input Button;

    output Light;

    assign Light = ~Button;

endmodule

After finding the synthesis and compile button, everything from the coding end worked fairly well. ISE even gave out a useful RTL Schematic of this module.

With ISE, Xilinx included a very basic simulation software which is done via a timing diagram and a “Simulate Behavioral Model” selection option. I could not find any dynamic option which allows you to change the input waveform and have the output waveforms change immediately w/o running the “Simulate Behavioral Model” selection.

For the most part, everything was going smoothly until I got to the floorplanning stage. Unfortunately, this is where things turned south. Apparently, ISE's PACE, it's floorplanning software, doesn't have a GUI option for me to select the pins for input and output of the CPLD. In order to do that, I had to manually go into the “user constraint file” or UCF and type out the pin connection as shown below.

#PINLOCK_BEGIN

#Fri Aug 09 14:59:15 2002

NET "Button" LOC = "S:PIN143";

NET "Light" LOC = "S:PIN92";

#PINLOCK_END

It took quite a bit of time to figure out how to do this and was completely unexpected. For this review, I did not do any timing constraints or have any major layout issues so I could not test how efficiently ISE routes through the functional blocks and macrocells.

When I finally got to the point of programming the CPLD, it went through without any problems. It was one of fastest and easiest programming experience I had with a device.

In Closing:

Overall, Xilinx's ISE software provides a way for us to design Xilinx hardware. It is a usable piece of software which has a fairly large learning curve due to it's UI uniqueness. This task took me a lot longer with most my time spent figuring out how the UCF file worked. During that time ISE also crashed a few times. For the most part, I think ISE still has quite a lot to work to go through before I can call it stable and user friendly, but for most work, it is a usable piece of software that Xilinx made and best of all, it's free.

Just A Reminder: This was a "Quick First Look" where I spent a few hours with this program.  Long term usage and satisfaction with this software may vary depending on the person, application, and design.  Please look at various different options before choosing any one technology for your design or product. 

References:

Xilinx XC2C256 CoolRunner-II CPLD Data Sheet: http://www.xilinx.com/support/documentation/data_sheets/ds094.pdf

Xilinx Design Suite 10.1 In-Depth Tutorial: http://direct.xilinx.com/direct/ise10_tutorials/ise10tut.pdf

Digilent XC2-XL Reference Manual, Schematic, and Board Verfication: http://www.digilentinc.com/Products/Documentation.cfm?Nav1=Products&Nav2=Documentation